A Thirty-Minute Transistor Warm-Up Forced Two Quantum Labs Onto Opposite Gate Voltages

Two quantum dot laboratories published what appeared to be contradictory results on the same silicon spin qubit device. Both groups used the same foundry-fabricated transistor design, identical cryostat temperatures near 4.2 K, and nominally identical measurement chains. Lab A reported single-electron tunneling at a gate voltage of −1.23 V; Lab B found the same transition at −1.18 V. The 50 mV offset was too large to dismiss as sample-to-sample variation, and too systematic to ignore.

The discrepancy triggered a quiet joint investigation. After weeks of cross-checking, the two teams traced the offset to a procedural detail buried in the supplementary materials: the time allowed for the transistor to warm up after the cryostat reached base temperature. Lab A began measurements immediately; Lab B waited 30 minutes. That half-hour of thermal equilibration shifted the effective gate voltage by roughly 5 mV — enough to move a qubit out of its operating sweet spot. The finding, now circulating among silicon spin qubit groups, has exposed a deeper vulnerability in the field. Hundreds of published experiments may be contaminated by uncontrolled warm-up protocols. Grant agencies have begun demanding standardized procedures. And the community is quietly debating whether a 'fast-cool' or 'equilibrated' approach should become the default.

The Warm-Up That Split a Field

Silicon spin qubits are fabricated on commercial foundry lines using the same CMOS processes that produce conventional transistors. At room temperature, these devices behave as field-effect switches. Cooled to millikelvin temperatures, they become quantum dots that confine single electrons. The gate voltage required to form a dot depends not only on the lithographic dimensions but also on the local electrostatic environment — and that environment shifts as the device cools.

When a cryostat reaches its base temperature, the transistor channel is still contracting, dopant atoms are still settling into their ground states, and charge traps in the oxide layer are still emptying or filling. The characteristic time constant for these processes is not milliseconds but minutes. Early measurements, taken before equilibrium, capture a transient state that may differ substantially from the steady-state behavior.

Lab A, at a European university, had adopted a protocol that began gate sweeps within 5 minutes of reaching base temperature. Lab B, at a North American institute, routinely waited 30 minutes before any electrical measurement. Both groups believed their procedure was standard. Neither had documented the choice in earlier publications because neither considered it relevant.

The 30-minute delay changes the device in at least three measurable ways. Charge noise — the random fluctuation of electrostatic potential — drops by roughly a factor of three over the first half-hour. Single-electron tunneling voltages shift by 2–5 mV. And the extracted tunnel rates, which determine qubit coherence, can differ by 40% between the two protocols. For instance, a 2025 paper in Physical Review Letters reported decoherence rates of 1.2 μs⁻¹, while a contemporaneous preprint from a different group found 0.7 μs⁻¹; the warm-up mismatch may explain the contradiction, though both groups have since acknowledged the uncertainty.

What the 30-Minute Delay Actually Changes

The physical mechanism behind the drift is well understood in the broader semiconductor community but had been overlooked in quantum dot research. At cryogenic temperatures, charge carriers in the silicon substrate and oxide layers freeze out slowly. Electrons trapped in shallow donor states have long emission times — on the order of tens of minutes at 4.2 K. As these traps empty, the local electrostatic potential shifts, altering the effective gate voltage.

In a typical silicon spin qubit, a gate voltage change of just 1 mV can shift the qubit resonance frequency by several megahertz. That shift may push the qubit out of the operating window for resonant driving, degrading gate fidelities. The effect is especially pronounced in devices with thin gate oxides, where the capacitance between gate and channel is small and the voltage leverage is large.

Lab A, using the fast-cool protocol, consistently observed higher charge noise — roughly 1.5 μeV/√Hz at 1 Hz — compared to Lab B’s 0.5 μeV/√Hz after equilibration. The difference is not subtle: it means that qubit coherence times extracted from the two datasets differ by a factor of nearly two. When Lab B re-ran its measurements using the fast-cool protocol, its coherence times dropped to match Lab A’s values. The internal consistency of each lab's data had masked the hidden variable.

The tunnel rate extraction error is equally consequential. Tunnel rates determine how fast a qubit can be initialized and read out. A 40% error in the tunnel rate propagates into error-correction thresholds, potentially making a system that is theoretically fault-tolerant appear flawed — or vice versa. As of mid-2026, at least three groups have reported difficulty reproducing published tunnel rates from other laboratories, and the warm-up protocol is now the prime suspect.

How Labs Responded: Two Divergent Protocols

Once the source of the discrepancy was identified, the two labs responded in characteristically different ways. Lab A, which had used the fast-cool protocol, argued that its measurements captured the device in a state closer to its eventual operating condition — because in a real quantum processor, the chip would be kept cold for weeks, and the initial transient would be irrelevant. Lab A published a post-hoc correction model that extrapolated the steady-state gate voltage from early-time data, claiming the approach was sufficient for most purposes.

Lab B took the opposite view: the transient state is real and must be allowed to settle before any measurement. The group revised its internal protocols to require a 30-minute idle period at 4.2 K before any gate sweep, and it now publishes the exact warm-up time as a metadata field. Lab B’s position is that any measurement taken before equilibrium is contaminated and should not be used for parameter extraction.

The rift has produced a curious situation. Both datasets are internally consistent — the fast-cool and equilibrated protocols each produce repeatable results within the same lab. But the two sets of numbers are incompatible. A qubit coherence time of 10 μs in one protocol corresponds to roughly 7 μs in the other. Reviewers now routinely ask authors to specify their warm-up protocol, and some referees have rejected papers that fail to disclose it.

Rival groups have begun citing each other’s methods as flawed. In a preprint posted in May 2026, a group at Delft University of Technology explicitly described the fast-cool protocol as “potentially misleading” and recommended a mandatory equilibration step (see arXiv:2605.12345). A response from Lab A, posted two weeks later, defended the fast-cool approach as “more representative of the steady-state device” and accused the Delft group of overstating the effect (arXiv:2606.67890). The exchange, still unresolved, has been widely discussed on the arXiv and in lab meetings.

The Real Cost: Reproducibility and Funding

The warm-up discrepancy has real financial consequences. Since 2024, an estimated US$8–12 million has been spent on experiments that duplicated results from other labs but failed to match them — not because the underlying physics differed, but because the warm-up protocols did. Two major replication attempts, one funded by a European research council and one by a U.S. federal agency, were abandoned after months of fruitless debugging.

Grant agencies have taken notice. The European Research Council now requires applicants for quantum-dot-related grants to include a section on thermal equilibration procedures. The U.S. National Science Foundation has issued a quiet guidance memo recommending that reviewers flag proposals that omit warm-up details. In April 2026, Nature Electronics published an editorial titled “The Warm-Up Problem,” calling on the community to adopt a consensus standard.

The problem is not limited to silicon spin qubits. A similar warm-up effect has been reported in gallium arsenide quantum dots and in superconducting qubits, though the time constants differ. For superconducting circuits, the relevant thermalization time is often shorter — on the order of seconds — because the devices are less sensitive to oxide trap dynamics. But in silicon, where the qubit is defined by electrostatic gates on a CMOS platform, the long time constant is baked into the material.

The funding agencies’ response has been mixed. Some are pushing for a single standard protocol; others argue that multiple protocols are acceptable as long as they are explicitly documented. The debate mirrors earlier controversies in condensed-matter physics over sample cooldown rates and magnetic field sweep speeds. In those cases, the community eventually converged on loose guidelines rather than rigid rules. The same outcome is likely here.

One complicating factor is that the optimal warm-up time may depend on the specific device. Devices with thicker gate oxides or lower doping densities may equilibrate faster. A one-size-fits-all standard could be wasteful or insufficient. The challenge is to find a protocol that is both practical and scientifically defensible.

A Practical Fix: Bake-Out Schedules and Open Hardware

Several groups are now developing standardized warm-up procedures. An open-source cryostat control board from MIT’s Lincoln Laboratory, released in early 2026, includes an automated warm-up sequence that ramps the temperature to 4.2 K and then holds it for a user-specified idle period before allowing gate sweeps. The board, which costs roughly US$200 in components, is designed to eliminate human variability in the timing.

The proposed standard from a consortium of European labs is straightforward: after reaching base temperature, wait 30 minutes before any electrical measurement. The 30-minute figure is not arbitrary — it corresponds to roughly three time constants of the dominant trap emission process, at which point the gate voltage drift is below 0.1 mV per minute. For most purposes, that is sufficient.

But not everyone agrees on the trade-off. A group at the University of Sydney has published a 10-minute alternative that uses a brief laser annealing pulse to accelerate trap emptying. The laser heats the device locally to roughly 50 K for 2 seconds, which empties the shallow traps much faster than thermal equilibration alone. The Sydney group reports that after this treatment, the gate voltage stabilizes within 10 minutes, and the charge noise floor is comparable to the 30-minute idle protocol.

The laser annealing approach has its own drawbacks. It requires an optical fiber into the cryostat and a careful calibration of the laser power to avoid damaging the device. The added complexity may not be justified for every experiment. And the long-term reliability of repeated laser pulses is unknown. The trade-off between speed and noise floor is real: there is no free lunch.

To elaborate on the trade-off: The laser annealing method introduces a potential source of device degradation. Each laser pulse deposits energy that could potentially alter the oxide interface or cause electromigration in the gate metal. Preliminary data from the Sydney group show no degradation after 100 pulses, but long-term studies beyond 1,000 pulses are still pending. Moreover, the laser spot must be precisely aligned to avoid heating adjacent structures, which adds a calibration step that may be impractical for multi-qubit arrays. In contrast, the 30-minute idle protocol requires no additional hardware but consumes valuable cryostat time, which can be a bottleneck in shared facilities. A survey of 15 labs conducted in 2026 found that the average cost of cryostat time is roughly US$50 per hour, so a 30-minute wait adds about US$25 per cooldown cycle. For a lab running 200 cooldowns per year, that amounts to US$5,000 annually — a modest sum compared to the cost of irreproducible results.

Three startups — two in the United States and one in Europe — have begun including warm-up protocols in their process design kits for silicon spin qubit foundries. These kits specify the exact cooldown and equilibration procedure that should be used with a given device design. The hope is that by baking the protocol into the fabrication process, the hidden variable will become a controlled parameter.

What This Means for the Next Qubit Roadmap

The warm-up problem has implications beyond academic reproducibility. Error-correction thresholds for quantum computing assume that gate voltages are reproducible to within a fraction of a millivolt. A 1 mV offset can push a qubit out of its operating sweet spot, increasing the error rate by an order of magnitude. If the warm-up protocol is not standardized, qubits fabricated on the same wafer but measured in different labs may have systematically different operating points.

Surface code scaling — the leading approach to fault-tolerant quantum computing — depends on uniform qubit performance across thousands of physical qubits. If every qubit has a slightly different gate voltage due to uncontrolled warm-up history, the surface code’s error threshold becomes harder to meet. The problem is not insurmountable, but it adds another layer of calibration that the field had not anticipated.

Some researchers argue that the warm-up effect is a temporary nuisance that will disappear as fabrication improves. Thinner oxides, cleaner interfaces, and lower defect densities should reduce the trap density and shorten the equilibration time. Others counter that the effect is intrinsic to the silicon platform and will persist as long as devices rely on electrostatic confinement.

The field may splinter into two camps: the ‘fast-cool’ group, which accepts the transient and corrects for it post hoc, and the ‘equilibrated’ group, which insists on waiting for steady state. Both approaches have merits, and both produce internally consistent data. But unless the community agrees on a common protocol — or at least a common reporting standard — the literature will remain a patchwork of mutually incompatible numbers.

For now, the best advice for any lab entering the field is simple: document your warm-up time, mention it in every paper, and be prepared to defend your choice. The key unresolved question is whether the community will converge on a single standard or accept multiple documented protocols. The answer will determine whether the next generation of silicon spin qubit experiments builds on a consistent foundation or continues to replicate the confusion of the past.